I'm going to now talk to you
about heterogeneous integration. In this video, I'll cover the basics of
Roadmapping Heterogeneous Integration for Interconnects. What I mean by that is, I'm going to
describe how you can define a roadmap where various stages of interconnect
scaling, or interconnect evolutions can be described, so that everybody
has a common path by which they can figure out how to improve heterogeneously
integrated components, okay? I'll focus on interconnect because that
is probably a very important aspect of advanced packaging, and I'll focus on
the advanced packaging because this, as I said, is the tip of the spear, okay? So let's start with a very
high level definition. If you have a package
where these components are connected laterally on
the package in the 2D plane, we call these interconnects
the 2D interconnects, okay? And if we now consider stacks where
the interconnect is connected in this direction, the vertical direction,
we call them 3D interconnects. Now this is a very high level
definition of the word interconnect, because there is obviously
a lot of complexity. But for this discussion it suffices to
think about interconnects in the XY plane, which I will call 2D, and in the Z plane,
which I will call 3D,okay? The whole point of interconnect definition
is to make sure that High Bandwidth, which is a large amount of data, Low Power,
when you transmit the data, is enabled. And it is well known in the industry
that these have to be the so called Parallel Links, which means you
must send data across multiple lanes, either vertically horizontally,
or both, okay? To be able to enable these parallel links, to keep the power low, and
to maintain high bandwidth, it is logically obvious that you
require high density of interconnects. And the driving vision in most packaging
is, if I put a lid on top of this device, you should not be able to distinguish
whether it is a SOC, which is a homogeneously integrated chip, or
an SIP, an integrated chip on a package. Which means these interconnects
must perform more or less the same, whether they are implemented on package or
implemented on the chip. So continuing the definition,
look at what a package typically does. You have a package which has pads, a die with bumps sits on those pads and
is connected, and then signals leave the edge of the die and
are fanned out. So if you go by this logic argument, and you look at how to define interconnect
density, you have two vectors. The first vector is,
how many interconnects can escape out of the edge of the die in
a horizontal fashion, okay? To increase the number of interconnects
that escape from the edge of the die, you have to reduce the width of the wire, you have to reduce the width of
the space between the wires, right? And in a package, what happens is
you have got multiple layers that are stacked on top of each other. So, connections between layers usually
happen with physical interconnects called vias that land on pads. In an ideal world, which can be
implemented, if you reduce the size of the pad to be zero, as in you land
the via right on top of the wire, you get the maximum amount
of wire intensity, okay? In addition, if you want to increase the
number of connections between the die and the package, you have to reduce
the pitch of the connections or the bump pitch, okay? So now with this logic argument, you have two physical metrics that you
can use to define interconnect density. The first is what we call
a linear interconnect density, which is the number of wires ,oftentimes
in the field they are called IO, so we will use that term as well, but the
number of wires that escape per millimeter of die edge on per layer of the package,
because there are multiple layers. That becomes a linear
interconnect density. And then there is the aerial
interconnect density, which is the number of bumps per
millimeter square of the die, okay? So let's start looking at
the Planar Interconnects, the number of interconnects on
each plane of a package, okay? I now define a very simple metric,
which is easy to understand logically. If you had a pad, and you went from
the pad through the space half the pad, the space and half the line,
you get a half line pitch, okay? And, you look at what are the different
technologies available in the market today that allow you to
get different interconnect density. So if you take a look at the workhorse
in this industry, the so called FCBGA, the flip chip
organic ball grid array package, traditional organic packages over
the years have evolved tremendously, and can give you somewhere in
the 30 to 50 wires per millimeter of die-edge per layer of the package. These are created by printing wires. So if you start printing finer and finer wires by optimizing the focus
of your printing technology, you can continue to increase the density,
and these are the so called high density organic interposes,
by shrinking the wires, shrinking the space between the wires,
and reducing the pad size to zero. For a two micron line and
a two micron space, you can get as high as
250 wires per millimeter. So this is a significant improvement
over the 50 to 30 we talked about. If ,on the other hand, you make use
of silicon printing technologies, in silicon typically, the VR pad,
the pad on which you print a VR, is the same width as the wire itself,
as in they are called the zero VR pads. You can get a tremendous
amount of wiring density. You can start with very coarse wiring, which is typical of the coarseness
of silicon printing at two microns. You start at 250 wires per millimeter
with two micron wires in space. You can continue to shrink the width
of the wire in the space to one micron that gives you 500 wires, you can go to
half a micron that gives you 1000 wires. So you notice that as you start moving
towards silicon class of technologies for wiring, you get tremendous
increases in wiring density. There are two broad classes of
technology that use this principle. One is the so called CO-AX Technology,
or the Silicon Interposer Technology, where you use a silicon interposer
on which you place your die. And the second is the EMIB technology, which does the same thing except in
only localized areas to get improvement. And if you now look at the picture on
the bottom left, by increasing these kind of wiring densities,
you can enable significantly improved, high bandwidth, low power,
parallel links between different die. And this has been realized by the HB or
the high bandwidth memory technologies to continually improve
memory bandwidth to compute. So the focus in all of this work is
to work on the physical layouts and reduce the density, to work on
the electrical layouts to be able to reduce the power and
essentially improve power, improve increased bandwidth by both
density and IO circuit improvements, okay? If we now move to
the vertical interconnects, we typically start with the bump pitch,
a much simpler metric. And this graph on the left shows
you that you can take solder based interconnects and continue to shrink them. And as you continue to shrink them,
because the density increases as an inverse function of the pitch, you get
tremendous improvements in the IO per millimeter square, or
the bumps per millimeter square. It is also fairly well known that
somewhere in the 20 25 micron regime, the solder based interconnects are going
to, quote and quote, run out of steam. Which means it will not be easy
to shrink them further down, especially as die sizes increase, okay? But we already know that there is
a technology called hybrid bonding, where you take copper and you connect it
to copper using a different technology for attach that allows you
to shrink the pitch. And you can continue to shrink the pitch. There is existence proof that you
can manufacture these at scale, at nine microns. And that's just the beginning, you can
scale that pitch down significantly. Two key points come out of this. First is that you can shrink
the bump pitch continually and get significant improvements
in IO per millimeter square. And somewhere in the 20 25ish regime, there is a transition from solder
to copper interconnect, okay?. Now that you know how to increase
the interconnect density by shrinking pitches in the XY and, it is obvious that
you can combine all of them together and create an architecture that blends these,
the 2D and the 3D. And this is an example
of such an architecture. For instance, you can take multiple
top die, connect them at less than 50 micron bump pitch on top of each other,
and then connect them on the sides. And you can create an architecture
that looks like the Ponte Vecchio. You have easily beaten the reticle size
limitations, you can create localized high density links using EMIB, and this allows
you to take multiple different devices, each optimized on that process and stitch them through high density,
high bandwidth, low power interconnects. And that's what these different
colors are supposed to represent, different kinds of die. And this leads you to Ponte Vecchio
which I described in a previous video. The Ponte Vecchio is a technological
marvel in this sense, it has greater than 100
billion transistors, 47 active tiles,
five different process nodes. It has compute memory, high density
interconnect, based on a different IO tile, it connects to different
high bandwidth memory connections, and it is all put together in
a relatively small package, okay? So in conclusion,
what you must realize out of this video is that interconnect scaling
can enable complex MCPs. And when you have complex MCPs,
you have tremendous performance advantage.